From the viewpoint of high-speed driving and reduction in cost, expectations have been focused on a Cu-based wiring layer having a lower resistivity than that of an Al-based wiring layer which is the mainstream of a wiring layer for a TFT panel at present.
However, there are problems in that Cu is inferior in an adhesion property to underlying substrate materials such as glass, Si, and the like, compared to adhesion properties of wiring materials such as Al and the like, and Cu is diffused to an underlying substrate.
In order to overcome such problems, a Cu wiring was developed in which an oxide layer of a Cu alloy was formed on a glass substrate or an amorphous Si substrate and a layer of Cu alone or a Cu alloy was formed thereon, by a method of sputtering a Cu alloy in an oxygen atmosphere (see, for example, Non-Patent Document 1). In this wiring layer, the layer of Cu alone or the Cu alloy secures a low electrical resistance, and the oxide layer of the Cu alloy enhances the adhesion of the interface between the Cu wiring and an underlying substrate, and in addition, the oxide layer of the Cu alloy serves as a barrier layer for preventing Cu from being diffused to the underlying substrate.
With regard to the wiring layer in which a Cu alloy is used, wiring layers which contain a variety of additive elements are proposed (see Patent Documents 1 and 2).
These Patent Documents disclose a technique in which a pure copper target (or a target in which at least one selected from Mg, Al, Si, Be, Ca, Sr, Ba, Ra, Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, and Dy is added) is sputtered while introducing oxygen gas so as to form a barrier layer which contains copper as a main component and oxygen, and then the introducing of the oxygen gas is stopped, and the above-mentioned target is sputtered so as to form a low-resistivity layer of pure copper. The above-mentioned barrier layer which contains copper as a main component and oxygen has a high adhesion property to silicon and glass and a low electrical resistance, and the barrier layer also prevents copper from being diffused to a silicon substrate.
In the wiring layer formed as mentioned above, a wiring layer pattern is formed as follows. An opening is formed in a resist film along a predetermined pattern, and a material of the wiring layer exposed to the opening is removed by dry or wet etching. As a result, a portion of an underlying layer becomes in an exposed state.
It is known that in the case where the above-mentioned Cu wiring layer pattern is formed on a non-single crystal semiconductor thin film such as an amorphous silicon thin film or a polycrystalline silicon thin film and a portion of the semiconductor thin film is exposed, a large number of dangling bonds (bonding partners which are not involved in a bond due to losing their covalent bonding partners) exist in the surface of the exposed semiconductor thin film The dangling bonds are unstable. Therefore, a hydrogen plasma treatment is generally conducted so as to terminate and stabilize the dangling bonds after the wiring layer pattern (source and drain electrode and the like) is formed in a process of manufacturing a semiconductor element (such as a TFT) which includes the non-single crystal semiconductor thin film.
The following phenomenon is reported which occurs in the hydrogen plasma treatment. Hydrogen ions easily infiltrate and penetrate into the wiring layer. Then, the oxide layer of the Cu alloy is reduced, and the reduced oxygen is bonded to hydrogen to generate water (water vapor). As a result, the layer is peeled off at the interface and the adhesion property is deteriorated (see, for example, Non-Patent Document 2).
Therefore, the development of a Cu wiring layer having a high hydrogen plasma resistance (resistance to hydrogen plasma) is required in which troubles such as the deterioration of the adhesion property do not occur after the above-mentioned hydrogen plasma treatment.